In less than a decade, artificial intelligence (AI) has gone from an obsession of a few ivory tower academics to runaway business success, potentially adding around US$13 trillion to the worldwide economy by 2030 in accordance with a McKinsey projection.
One motive that AI is taking off now rather than when it was first conceptualized in the late Fifties is the availability of inexpensive computational power, in turn, made possible by steady advances in chip design.
However, for all the technological advances ever smaller and powerful integrated circuits (IC) have ushered in, designing the chips themselves remains a time-consuming and labor-intensive process. Although electronic design automation (EDA) software automating the placement of transistors on a chip has been available since the Eighties, the input of experienced human engineers continues to be required in what is largely a trial-and-error course, along with EDA tools to search out the optimized sweet spot.
In a virtuous circle, a crew of A*STAR researchers from IME and the Institute for Infocomm Research (I²R) has now built a machine studying framework which works in tandem with the EDA instruments to capture the experience of seasoned chip developers, using it to reduce the cost of designing new chips whereas simultaneously exploring new design areas.